Intel's Ivy Bridge series of central processing units has been the topic of many rumors and leaks recently, but its die layout has not been disclosed yet.
That did not stop Hiroshige Goto, contributor for PC Watch, from estimating it and the configurations it would allow for.
According to him, the layout is the same as the one exhibited by the Sandy Bridge collection.
The central portion has four x86-64 cores, each with 256 KB of dedicated L2 cache memory. All are connected by 8 MB of shared L3 cache.
On the sides of the central portion lie the system agent and the graphics core, the HD 4000 which behaves up to 122.1% better in benchmarks compared to SB's HD 3000.
The system agent includes a PCI Express controller, the DMI chipset bus and the interface for dual-channel DDR3 memory.
What binds all these separate entities together is a ring-bus, which transports data between the CPU cores, L3 cache and system agent.
All in all, the die area should be of roughly 166 square millimeters (160 mm²) and the total transistor count should be of 1.48 million.
That is physically smaller than the 216 mm² Sandy Bridge area, but the transistor count is superior (SB has only 1.16 billion).
The graphics core has up to 16 programmable EUs (for parallel processing) and can carry out GPGPU tasks as well.
Meanwhile, the ring bus uses “ring-stops” to pick up and drop off data, maintains DMI and FDI links to PCH, includes a display controller and can even direct the PCI Express interface to drive one x16 slot or two x8 slots.
All in all, Intel can set up the silicon in four ways: a quad-core with 8 MB L3 cache and all 16 shader cores operational, a quad-core with 6 MB L3 cache and fewer shaders, a dual-core with 4 MB L3 cache and all shaders cores and, finally, a dual-core with 3 MB L3 and fewer IGP shaders enabled.