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Sep 26, 2011

AMD FX-8170 and FX-6120 Processors to Arrive in Early 2012

Even though there are still two weeks to go until AMD will release its first FX-Series processors into the wild, reports suggest the Sunnyvale-based chip maker is already planning to introduce faster versions of these chips in the first quarter of 2012.

According to a recently leaked company roadmap, the start of 2012 will mark the introduction of two new FX-Series CPU that are referred to as the FX-8170 and the FX-6120.

Just as its name implies, the FX-8170 is a faster version of the FX-8150 that will launch on October 12 and it boasts four Bulldozer modules to deliver a total of eight computing cores.

These will be accompanied by 8MB of Level 3 as well as 8MB of L2 cache memory, but the rest of its specifications haven't been finalized yet.

However, the Donanim Haber Website states sources familiar with AMD's plans informed them that the chip will be clocked at least 200MHz higher than the FX-8150, which has a base operating frequency of 3.6GHz.

Moving to the FX-6120, its base and Turbo clock speeds are also unknown, but the CPU will include six processing cores backed by 6MB of Level 2 cache as well as by 8MB of L3 cache, just as its the case with its older brother.

When the two new AMD desktop Bulldozer processors will arrive, they will have to compete with a new series of Intel CPUs based on the high-performance Sandy Bridge-E architecture.

These are expected to be launched in mid-November, and will have no trouble in surpassing the FX-8150, if the leaked AMD press deck benchmarks we reported about earlier are indeed true.

In development since 2005, Bulldozer is AMD's next high-performance processor architecture, and is optimized to deliver better inter-core communications and a higher instructions per clock cycle count.

As a result, AMD used a modular approach, each dual-core module being comprised of 2MB of L2 cache, 16kB 4-way L1 data cache per core and a 2-way 64kB L1 instruction cache per module, two dedicated integer cores and two symmetrical 128-bit FMAC pipelines that can be unified into one large 256-bit wide unit.


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