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Aug 28, 2012

AMD Jaguar Presented Today

The Hot Chips conference is taking place right now; there, AMD is introducing the new Jaguar APU architecture that's going to replace the current Bobcat cores in the company’s low-power APUs. The new design brings considerably increased IPC (instructions per clock) capabilities along with support for new compute instructions.

We already know that some of the new instruction sets that will come inside AMD’s new microprocessor design are AVX, BMI, SSE 4.2 and AES. Jaguar will be quite different from Bobcat, as it will likely have a unified 2MB cache and will probably use AMD’s second-generation GCN architecture. The thing is that Jaguar in itself is the x86 processing core design that will be integrated in the upcoming Kabini and Temash APUs.

The company will be free to pair the new Jaguar cores with VLIW iGPUs or GCN-based graphics. The x86 computing cores will be seriously modified. The IPC will be increased and the company will add support for TBM instructions.

AMD Ontario Die Shot
Image credits to Anandtech


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