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Mar 19, 2014

AMD Carrizo APU Leaked, Has DDR4, but Is Crippled in PCI Express Support




AMD's Kaveri accelerated processing unit, sold under the A-Series brand, was released back in January, and will be succeeded in 2015 by Carrizo, whose preliminary specs have just been uncovered.

Bright Side of News, BSN for short, somehow uncovered some of the information regarding the next-generation APU. As you may know, the Kaveri is powered by the Steamroller architecture, or at least the central processing unit cores are. The GPU part, 8 SP modules based on Graphics Core Next, take up more of the die than the four CPU cores themselves, but we digress. For the first time, AMD will implement a full Fusion Control Hub in the APU, on on-die southbridge so to speak. The FCH will only have two SATA 6.0 Gbps ports though, four USB 3.0 ports and four USB 2.0 connectors. It sounds like a shame at first glance, since the southbridge (or what used to be called that) would normally be able to handle much more than this.

But then you reach the part where it says that the FCH will only be active on mobile variants of the processors. That's right, Advanced Micro Devices is preparing Carrizo chips for tablets and (maybe) mobile phones. This must be why power efficiency will be a key concern. The onboard FCH will actually deactivate when you install the Carrizo APU inside an FM2+ socket. The motherboard's own Fusion Controller Hub will enter the fray then, providing many more storage and connectivity interfaces than the on-die one. Another important asset of Carrizo is the support for not just DDR3 RAM, but also DDR4 memory. We don't have any clock speed info, but even the assurance that DDR4 will be available is better than nothing, since it would have been truly unfortunate if Intel was the only one with that interface.

No mention of a GDDR5 controller suggests that dual-DDR4 channel memory might be what AMD has planned for backing up the on-board GPU (51.2 GB/s bandwidth, vs. 38.4 GB/s for DDR3-2400). Other features include support for AVX2 instructions (full 256-bit registers, probably), and a random number generator. Finally, and this could be a problem, 16 PCI Express lanes are available, down from 24, which implies that no more than a single PCI Express x8 slot will be possible to implement, or two in x4 electrical mode. It kind of kills the prospects of multi-GPU configurations, but is sufficient for any add-in card, and AMD might be trying to nudge people towards Dual Graphics anyway (where the APU GPU joins forces with the add-in card). It might damage marketability if AMD doesn't advertise the features right though.

AMD Carrizo APU detailed
Image credits to AMD

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